24 search results - page 4 / 5 » Exploiting a Computation Reuse Cache to Reduce Energy in Net... |
LCTRTS
2007
Springer
13 years 11 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents a new methodology for implementing fast synchronization on scalable cache-coherent multiprocessors, through the use of hybrid primitives. Hybrid primitives lev...
COMCOM
2004
13 years 5 months ago
2004
Storage, memory, processor, and communications bandwidth are all relatively plentiful and inexpensive. However, a growing expense in the operation of computer networks is electric...
PDP
2010
IEEE
13 years 9 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
RTAS
2005
IEEE
13 years 11 months ago
2005
IEEE
Dynamic voltage and frequency scaling is increasingly being used to reduce the energy requirements of embedded and real-time applications by exploiting idle CPU resources, while s...