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DATE
2004
IEEE
114views Hardware» more  DATE 2004»
11 years 9 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
PLDI
2003
ACM
11 years 10 months ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, signi´Čücant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
DAC
2010
ACM
11 years 9 months ago
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme
System optimization techniques based on dynamic voltage scaling (DVS) are widely used with the aim of reducing processor energy consumption. Inter-task DVS assigns the same voltag...
Weixun Wang, Prabhat Mishra
SOSP
2001
ACM
12 years 2 months ago
Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems
In recent years, there has been a rapid and wide spread of nontraditional computing platforms, especially mobile and portable computing devices. As applications become increasingl...
Padmanabhan Pillai, Kang G. Shin
ICS
2005
Tsinghua U.
11 years 10 months ago
Low-power, low-complexity instruction issue using compiler assistance
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S...
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