7 search results - page 1 / 2 » Exploiting level sensitive latches in wire pipelining |
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
CAL
2004
13 years 4 months ago
2004
Wires shrink less efficiently than transistors. Smaller dimensions increase relative delay and the probability of crosstalk. Solutions to this problem include adding additional lat...
ASYNC
2002
IEEE
13 years 9 months ago
2002
IEEE
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
MICRO
2003
IEEE
13 years 9 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...