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SAC
2008
ACM
10 years 11 months ago
Exploiting program cyclic behavior to reduce memory latency in embedded processors
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
Ehsan Atoofian, Amirali Baniasadi
CASES
2004
ACM
11 years 5 months ago
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems
A coarse-grain multithreaded processor can effectively hide long memory latencies by quickly switching to an alternate task when the active task issues a memory request, improving...
Ali El-Haj-Mahmoud, Eric Rotenberg
ASPLOS
2008
ACM
11 years 2 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
ICS
2000
Tsinghua U.
11 years 3 months ago
Hardware-only stream prefetching and dynamic access ordering
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...
Chengqiang Zhang, Sally A. McKee
DAC
2002
ACM
12 years 29 days ago
Exploiting shared scratch pad memory space in embedded multiprocessor systems
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we p...
Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhar...
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