41 search results - page 1 / 9 » Exploiting program cyclic behavior to reduce memory latency ... |
SAC
2008
ACM
13 years 4 months ago
2008
ACM
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
CASES
2004
ACM
13 years 10 months ago
2004
ACM
A coarse-grain multithreaded processor can effectively hide long memory latencies by quickly switching to an alternate task when the active task issues a memory request, improving...
ASPLOS
2008
ACM
13 years 6 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
ICS
2000
Tsinghua U.
13 years 8 months ago
2000
Tsinghua U.
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we p...