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» Exploiting refactoring in formal verification
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DSN
2009
IEEE
9 years 5 months ago
Exploiting refactoring in formal verification
Xiang Yin, John C. Knight, Westley Weimer
SIGSOFT
2003
ACM
9 years 11 months ago
Towards scalable compositional analysis by refactoring design models
Automated finite-state verification techniques have matured considerably in the past several years, but state-space explosion remains an obstacle to their use. Theoretical lower b...
Yung-Pin Cheng, Michal Young, Che-Ling Huang, Chia...
BCS
2008
8 years 11 months ago
Tools for Traceable Security Verification
Dependable systems evolution has been identified by the UK Computing Research Committee (UKCRC) as one of the current grand challenges for computer science. We present work toward...
Jan Jürjens, Yijun Yu, Andreas Bauer 0002
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
9 years 10 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
HVC
2007
Springer
106views Hardware» more  HVC 2007»
9 years 2 months ago
Exploiting Shared Structure in Software Verification Conditions
Abstract. Despite many advances, today's software model checkers and extended static checkers still do not scale well to large code bases, when verifying properties that depen...
Domagoj Babic, Alan J. Hu
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