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ARCS
2010
Springer
11 years 8 months ago
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
Jörg Mische, Irakli Guliashvili, Sascha Uhrig...
ICCD
2008
IEEE
167views Hardware» more  ICCD 2008»
11 years 8 months ago
Exploiting spare resources of in-order SMT processors executing hard real-time threads
— We developed an SMT processor that allows a static WCET analysis of several hard real-time threads and uses the remaining resources for soft or non real-time threads. The analy...
Jörg Mische, Sascha Uhrig, Florian Kluge, The...
ISCA
1998
IEEE
124views Hardware» more  ISCA 1998»
11 years 5 months ago
Threaded Multiple Path Execution
This paper presents Threaded Multi-Path Execution (TME), which exploits existing hardware on a Simultaneous Multithreading (SMT) processor to speculatively execute multiple paths ...
Steven Wallace, Brad Calder, Dean M. Tullsen
CASES
2005
ACM
11 years 3 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
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