14 search results - page 2 / 3 » Exploring Area Delay Tradeoffs in an AES FPGA Implementation |
FPGA
1999
ACM
13 years 9 months ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
SASP
2008
IEEE
13 years 11 months ago
2008
IEEE
— Matrix inversion is a common function found in many algorithms used in wireless communication systems. As FPGAs become an increasingly attractive platform for wireless communic...
TC
2008
13 years 4 months ago
2008
This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In ...
SLIP
2006
ACM
13 years 11 months ago
2006
ACM
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
FPL
2007
Springer
13 years 11 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...