Sciweavers

21 search results - page 2 / 5
» Exploring Fault-Tolerant Network-on-Chip Architectures
Sort
View
SC
2005
ACM
13 years 10 months ago
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer
As device scales shrink, higher transistor counts are available while soft-errors, even in logic, become a major concern. A new class of architectures, such as Merrimac and the IB...
Mattan Erez, Nuwan Jayasena, Timothy J. Knight, Wi...
ASPLOS
2006
ACM
13 years 11 months ago
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance
Redundant threading architectures duplicate all instructions to detect and possibly recover from transient faults. Several lighter weight Partial Redundant Threading (PRT) archite...
Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasa...
ASAP
2007
IEEE
153views Hardware» more  ASAP 2007»
13 years 5 months ago
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
Haibo Zhu, Partha Pratim Pande, Cristian Grecu
PPOPP
2005
ACM
13 years 10 months ago
Fault tolerant high performance computing by a coding approach
As the number of processors in today’s high performance computers continues to grow, the mean-time-to-failure of these computers are becoming significantly shorter than the exe...
Zizhong Chen, Graham E. Fagg, Edgar Gabriel, Julie...
CORR
2011
Springer
166views Education» more  CORR 2011»
12 years 9 months ago
An Overview of Portable Distributed Techniques
In this paper, we reviewed of several portable parallel programming paradigms for use in a distributed programming environment. The Techniques reviewed here are portable. These ar...
Sanjay Bansal, Nirved Pandey