29 search results - page 6 / 6 » Exploring SW Performance Using SoC Transaction-Level Modelin... |
DT
2006
13 years 4 months ago
2006
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
SBCCI
2005
ACM
13 years 10 months ago
2005
ACM
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy c...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...