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DATE
2009
IEEE
139views Hardware» more  DATE 2009»
13 years 11 months ago
Cross-architectural design space exploration tool for reconfigurable processors
—Processors that deploy fine-grained reconfigurable fabrics to implement application-specific accelerators ondemand obtained significant attention within the last decade. They tr...
Lars Bauer, Muhammad Shafique, Jörg Henkel
ISPASS
2006
IEEE
13 years 10 months ago
Accelerating architectural exploration using canonical instruction segments
Detailed microarchitectural simulators are not well suited for exploring large design spaces due to their excessive simulation times. We introduce AXCIS, a framework for fast and ...
Rose F. Liu, Krste Asanovic
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
13 years 9 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
VLSID
2009
IEEE
177views VLSI» more  VLSID 2009»
14 years 5 months ago
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...
Unmesh D. Bordoloi, Samarjit Chakraborty
APN
2004
Springer
13 years 10 months ago
An Approach to Distributed State Space Exploration for Coloured Petri Nets
Abstract. We present an approach and associated computer tool support for conducting distributed state space exploration for Coloured Petri Nets (CPNs). The distributed state space...
Lars Michael Kristensen, Laure Petrucci