13 search results - page 2 / 3 » FPGA Implementations of the Round Two SHA-3 Candidates |
SACRYPT
2009
Springer
14 years 1 days ago
2009
Springer
Abstract. In this paper we analyse the security of the SHA-3 candidate ARIRANG. We show that bitwise complementation of whole registers turns out to be very useful for constructing...
FSE
2011
Springer
12 years 9 months ago
2011
Springer
In this paper, we present new results on the second-round SHA-3 candidate ECHO. We describe a method to construct a collision in the compression function of ECHO-256 reduced to fou...
FSE
2010
Springer
13 years 10 months ago
2010
Springer
In this paper, we improve the recent rebound and start-from-the-middle attacks on AES-like permutations. Our new cryptanalysis technique uses the fact that one can view two rounds ...
CTRSA
2001
Springer
13 years 10 months ago
2001
Springer
The results of fast implementations of all five AES final candidates using Virtex Xilinx Field Programmable Gate Arrays are presented and analyzed. Performance of several alternati...
CEE
2004
13 years 5 months ago
2004
A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are u...