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DATE
2000
IEEE
139views Hardware» more  DATE 2000»
13 years 9 months ago
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
HICSS
2006
IEEE
131views Biometrics» more  HICSS 2006»
13 years 11 months ago
Design and Characterization of a Hardware Encryption Management Unit for Secure Computing Platforms
— Software protection is increasingly necessary for uses in commercial systems, digital content distributors, and military systems. The Secure Software (SecSoft) architecture is ...
Anthony J. Mahar, Peter M. Athanas, Stephen D. Cra...
IPPS
2003
IEEE
13 years 10 months ago
Architectural Frameworks for MPP Systems on a Chip
Advances in fabrication techniques are now enabling new hybrid CPU/FPGA computing resources to be integrated onto a single chip. While these new hybrids promise significant perfor...
David L. Andrews, Douglas Niehaus
FPL
2010
Springer
134views Hardware» more  FPL 2010»
13 years 3 months ago
GPU Versus FPGA for High Productivity Computing
Heterogeneous or co-processor architectures are becoming an important component of high productivity computing systems (HPCS). In this work the performance of a GPU based HPCS is c...
David Huw Jones, Adam Powell, Christos-Savvas Boug...