11 search results - page 1 / 3 » FPGA power reduction by guarded evaluation |
FPGA
2010
ACM
14 years 1 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
ISLPED
1995
ACM
13 years 7 months ago
1995
ACM
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
FPL
2009
Springer
13 years 8 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...