Sciweavers

7 search results - page 2 / 2
» FSMD Functional Partitioning for Low Power
Sort
View
TC
2008
13 years 4 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
INFOCOM
2005
IEEE
13 years 10 months ago
IPStash: a set-associative memory approach for efficient IP-lookup
—IP-Lookup is a challenging problem because of the increasing routing table sizes, increased traffic, and higher speed links. These characteristics lead to the prevalence of hard...
Stefanos Kaxiras, Georgios Keramidas