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» Fast Area Estimation to Support Compiler Optimizations in FP...
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FCCM
2002
IEEE
146views VLSI» more  FCCM 2002»
13 years 9 months ago
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker...
DSD
2005
IEEE
106views Hardware» more  DSD 2005»
13 years 10 months ago
SystemC-based Design Methodology for Reconfigurable System-on-Chip
Reconfigurable system is a promising alternative to deliver both flexibility and performance at the same time. New reconfigurable technologies and technologydependent tools have b...
Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen
DAC
2003
ACM
14 years 5 months ago
Data communication estimation and reduction for reconfigurable systems
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
Adam Kaplan, Philip Brisk, Ryan Kastner
CASES
2006
ACM
13 years 8 months ago
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
Won So, Alexander G. Dean
FCCM
2000
IEEE
122views VLSI» more  FCCM 2000»
13 years 9 months ago
Evaluating Hardware Compilation Techniques
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
Markus Weinhardt, Wayne Luk