8 search results - page 1 / 2 » Fast Cycle-accurate Behavioral Simulation for Pipelined Proc... |
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of ...
ISPASS
2007
IEEE
13 years 10 months ago
2007
IEEE
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
RTCSA
2007
IEEE
13 years 10 months ago
2007
IEEE
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...