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HPCA
2004
IEEE
14 years 4 months ago
Signature Buffer: Bridging Performance Gap between Registers and Caches
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
Lu Peng, Jih-Kwon Peir, Konrad Lai
ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
13 years 8 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
13 years 7 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...