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» Fast Inductance Extraction of Large VLSI Circuits
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ICCAD
1993
IEEE
121views Hardware» more  ICCAD 1993»
13 years 7 months ago
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
Arjan J. van Genderen, N. P. van der Meijs
TVLSI
2010
12 years 10 months ago
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling
To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp ...
Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He,...
ICCAD
1994
IEEE
115views Hardware» more  ICCAD 1994»
13 years 7 months ago
Fast transient power and noise estimation for VLSI circuits
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
Wolfgang T. Eisenmann, Helmut E. Graeb
ICCAD
2002
IEEE
108views Hardware» more  ICCAD 2002»
14 years 16 days ago
A precorrected-FFT method for simulating on-chip inductance
The simulation of on-chip inductance using PEEC-based circuit analysis methods often requires the solution of a subproblem where an extracted inductance matrix must be multiplied ...
Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushi...
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
13 years 8 months ago
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of ...
Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie...