5 search results - page 1 / 1 » Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI |
ARITH
2011
IEEE
12 years 4 months ago
2011
IEEE
— This paper presents a number of new high-radix ripple-carry adder designs based on Ling’s addition technique and a recently-published expansion thereof. The proposed adders a...
ARVLSI
2001
IEEE
13 years 8 months ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
ARITH
1999
IEEE
13 years 8 months ago
1999
IEEE
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
ISCAS
2008
IEEE
13 years 10 months ago
2008
IEEE
—In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient gen...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...