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    WSC
    1997
    151views Modeling And Simulation» more  WSC 1997»
    Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
    13 years 6 months ago
    Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
    Download  www.informs-sim.org
    We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
    Peter S. Magnusson
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    JVM
    2004
    165views Education» more  JVM 2004»
    Using Hardware Performance Monitors to Understand the Behavior of Java Applications
    13 years 6 months ago
    Using Hardware Performance Monitors to Understand the Behavior of Java Applications
    Download  www-plan.cs.colorado.edu
    Modern Java programs, such as middleware and application servers, include many complex software components. Improving the performance of these Java applications requires a better ...
    Peter F. Sweeney, Matthias Hauswirth, Brendon Caho...
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