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DATE
2005
IEEE
164views Hardware» more  DATE 2005»
13 years 5 months ago
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...
Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho S...
DAC
2004
ACM
13 years 9 months ago
Extending the transaction level modeling approach for fast communication architecture exploration
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 15 days ago
Fast and accurate transaction level models using result oriented modeling
Efficient communication modeling is a critical task in SoC design and exploration. In particular, fast and accurate communication is needed to predict the performance of a system....
Gunar Schirner, Rainer Dömer
ASPDAC
2009
ACM
249views Hardware» more  ASPDAC 2009»
13 years 8 months ago
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
Chen Kang Lo, Ren-Song Tsay
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
13 years 10 months ago
Fast and accurate protocol specific bus modeling using TLM 2.0
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
H. W. M. van Moll, Henk Corporaal, Víctor R...