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DAC
2004
ACM
10 years 5 months ago
Fast and accurate parasitic capacitance models for layout-aware
Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tabl...
Anuradha Agarwal, Hemanth Sampath, Veena Yelamanch...
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
10 years 5 months ago
A More Effective CEFF
Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for dr...
Sani R. Nassif, Zhuo Li
ICCAD
1996
IEEE
129views Hardware» more  ICCAD 1996»
10 years 3 months ago
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits
-- In this tutorial we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due toincreasing operating...
N. P. van der Meijs, T. Smedes
TVLSI
2002
144views more  TVLSI 2002»
9 years 11 months ago
On-chip inductance cons and pros
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Yehea I. Ismail
ISPD
2007
ACM
124views Hardware» more  ISPD 2007»
10 years 1 months ago
Accurate power grid analysis with behavioral transistor network modeling
In this paper, we propose fast and eļ¬ƒcient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for...
Anand Ramalingam, Giri Devarayanadurg, David Z. Pa...
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