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ASPDAC
2009
ACM
249views Hardware» more  ASPDAC 2009»
13 years 9 months ago
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
Chen Kang Lo, Ren-Song Tsay
DAC
2004
ACM
13 years 10 months ago
Extending the transaction level modeling approach for fast communication architecture exploration
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
13 years 11 months ago
Fast and accurate protocol specific bus modeling using TLM 2.0
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
H. W. M. van Moll, Henk Corporaal, Víctor R...
ASPDAC
2010
ACM
151views Hardware» more  ASPDAC 2010»
13 years 1 months ago
Source-level timing annotation for fast and accurate TLM computation model generation
This paper proposes a source-level timing annotation method for generation of accurate transaction level models for software computation modules. While Transaction Level Modeling ...
Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay
DATE
2006
IEEE
147views Hardware» more  DATE 2006»
13 years 10 months ago
Quantitative analysis of transaction level models for the AMBA bus
The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model ation in systems...
Gunar Schirner, Rainer Dömer