49 search results - page 2 / 10 » Fast buffer insertion considering process variations |
ICCD
2005
IEEE
13 years 11 months ago
2005
IEEE
— In this work we investigate the buffer insertion problem under process variations. Sub 100-nm fabrication process causes significant variations on many design parameters. We p...
DAC
2010
ACM
13 years 4 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
ISVLSI
2008
IEEE
14 years 16 days ago
2008
IEEE
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...
ISQED
2007
IEEE
14 years 13 days ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
DAC
2003
ACM
14 years 7 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...