56 search results - page 3 / 12 » Fast compiler optimisation evaluation using code-feature bas... |
CF
2004
ACM
13 years 11 months ago
2004
ACM
Next generation architectures will require innovative solutions to reduce energy consumption. One of the trends we expect is more extensive utilization of compiler information dir...
SLIP
2003
ACM
13 years 11 months ago
2003
ACM
In the past, a priori interconnect prediction, based on Rent’s rule, has been applied mainly for technology evaluation and roadmap applications. These applications do not requir...
SAMOS
2007
Springer
14 years 11 days ago
2007
Springer
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
CAL
2006
13 years 6 months ago
2006
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
RTAS
2010
IEEE
13 years 4 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...