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PDP
2011
IEEE
12 years 9 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
PODC
2010
ACM
13 years 9 months ago
The multiplicative power of consensus numbers
: The Borowsky-Gafni (BG) simulation algorithm is a powerful reduction algorithm that shows that t-resilience of decision tasks can be fully characterized in terms of wait-freedom....
Damien Imbs, Michel Raynal
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 9 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
CIKM
2007
Springer
13 years 11 months ago
Optimal proactive caching in peer-to-peer network: analysis and application
As a promising new technology with the unique properties like high efficiency, scalability and fault tolerance, Peer-toPeer (P2P) technology is used as the underlying network to b...
Weixiong Rao, Lei Chen 0002, Ada Wai-Chee Fu, Ying...