19 search results - page 1 / 4 » Fault Tolerant Network on Chip Switching With Graceful Perfo... |
TCAD
2010
12 years 11 months ago
2010
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
ETS
2011
IEEE
12 years 4 months ago
2011
IEEE
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
ISCA
2006
IEEE
13 years 4 months ago
2006
IEEE
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
IPPS
2003
IEEE
13 years 9 months ago
2003
IEEE
This work presents a new switching mechanism to tolerate arbitrary faults in interconnection networks with a negligible implementation cost. Although our routing technique can be ...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...