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SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
13 years 10 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
IEEECIT
2010
IEEE
13 years 3 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
ET
2008
92views more  ET 2008»
13 years 4 months ago
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
EDCC
2006
Springer
13 years 8 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
SOSP
2007
ACM
14 years 1 months ago
Tolerating byzantine faults in transaction processing systems using commit barrier scheduling
This paper describes the design, implementation, and evaluation of a replication scheme to handle Byzantine faults in transaction processing database systems. The scheme compares ...
Ben Vandiver, Hari Balakrishnan, Barbara Liskov, S...