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ET
2007
111views more  ET 2007»
13 years 5 months ago
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware
This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a...
Fatih Kocan, Daniel G. Saab
VTS
1999
IEEE
81views Hardware» more  VTS 1999»
13 years 10 months ago
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process...
Debashis Nayak, D. M. H. Walker
ICCAD
2006
IEEE
183views Hardware» more  ICCAD 2006»
14 years 2 months ago
Soft error derating computation in sequential circuits
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...
Hossein Asadi, Mehdi Baradaran Tahoori
GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
13 years 6 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...
ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
13 years 3 months ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng