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ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
13 years 9 months ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
ET
2000
145views more  ET 2000»
13 years 4 months ago
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
Jaan Raik, Raimund Ubar
DAC
1999
ACM
13 years 8 months ago
IC Test Using the Energy Consumption Ratio
Dynamic-current based test techniques can potentially address the drawbacks of traditional and Iddq test methodologies. The quality of dynamic current based test is degraded by pr...
Wanli Jiang, Bapiraju Vinnakota
CCGRID
2010
IEEE
13 years 5 months ago
Region-Based Prefetch Techniques for Software Distributed Shared Memory Systems
Although shared memory programming models show good programmability compared to message passing programming models, their implementation by page-based software distributed shared m...
Jie Cai, Peter E. Strazdins, Alistair P. Rendell
DSN
2009
IEEE
13 years 11 months ago
Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems
The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this pap...
Naga Durga Prasad Avirneni, Viswanathan Subramania...