Sciweavers

172 search results - page 35 / 35
» FinFET-based SRAM design
Sort
View
CF
2010
ACM
13 years 10 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
INFOCOM
2002
IEEE
13 years 10 months ago
Scalable IP Lookup for Programmable Routers
Abstract— Continuing growth in optical link speeds places increasing demands on the performance of Internet routers, while deployment of embedded and distributed network services...
David E. Taylor, John W. Lockwood, Todd S. Sproull...