Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
— In this work we investigate the buffer insertion problem under process variations. Sub 100-nm fabrication process causes significant variations on many design parameters. We p...
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Abstract—This paper describes a robust and accurate blackbox macromodeling technique, in which the constitutive equations combine both closed-form delay operators and low-order r...