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ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
14 years 2 months ago
Accurate estimation of global buffer delay within a floorplan
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
ISPD
1997
ACM
110views Hardware» more  ISPD 1997»
13 years 9 months ago
Performance driven global routing for standard cell design
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
Jason Cong, Patrick H. Madden
ICCD
2005
IEEE
90views Hardware» more  ICCD 2005»
13 years 10 months ago
Variability-Driven Buffer Insertion Considering Correlations
— In this work we investigate the buffer insertion problem under process variations. Sub 100-nm fabrication process causes significant variations on many design parameters. We p...
Azadeh Davoodi, Ankur Srivastava
ISPASS
2009
IEEE
14 years 11 hour ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
13 years 10 months ago
On the construction of guaranteed passive macromodels for high-speed channels
Abstract—This paper describes a robust and accurate blackbox macromodeling technique, in which the constitutive equations combine both closed-form delay operators and low-order r...
Alessandro Chinea, Stefano Grivet-Talocia, Dirk De...