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» Fixed-Polynomial Size Circuit Bounds
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ASPDAC
2007
ACM
123views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Coupling-aware Dummy Metal Insertion for Lithography
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip...
Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua ...
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
14 years 2 months ago
Obstacle-avoiding rectilinear Steiner tree construction
— In today’s VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important prob...
Liang Li, Evangeline F. Y. Young