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» Flexible pipelining design for recursive variable expansion
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IPPS
2009
IEEE
13 years 11 months ago
Flexible pipelining design for recursive variable expansion
Many image and signal processing kernels can be optimized for performance consuming a reasonable area by doing loops parallelization with extensive use of pipelining. This paper p...
Zubair Nawaz, Thomas Marconi, Koen Bertels, Todor ...
FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
13 years 9 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
EMSOFT
2006
Springer
13 years 8 months ago
Scheduling-independent threads and exceptions in SHIM
Concurrent programming languages should be a good fit for embedded systems because they match the intrinsic parallelism of their architectures and environments. Unfortunately, typ...
Olivier Tardieu, Stephen A. Edwards
ICFP
2001
ACM
14 years 5 months ago
Macros as Multi-Stage Computations: Type-Safe, Generative, Binding Macros in MacroML
With few exceptions, macros have traditionally been viewed as operations on syntax trees or even on plain strings. This view makes macros seem ad hoc, and is at odds with two desi...
Steven E. Ganz, Amr Sabry, Walid Taha
BMCBI
2006
132views more  BMCBI 2006»
13 years 5 months ago
Comprehensive quality control utilizing the prehybridization third-dye image leads to accurate gene expression measurements by c
Background: Gene expression profiling using microarrays has become an important genetic tool. Spotted arrays prepared in academic labs have the advantage of low cost and high desi...
Xujing Wang, Shuang Jia, Lisa Meyer, Bixia Xiang, ...