36 search results - page 4 / 8 » Floating Point Unit Generation and Evaluation for FPGAs |
FCCM
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
ARITH
2009
IEEE
14 years 8 days ago
2009
IEEE
In this work we propose new decimal floating-point CORDIC algorithms for transcendental function evaluation. We show how these algorithms are mapped to a state of the art Decimal...
ARC
2007
Springer
13 years 9 months ago
2007
Springer
Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical netwo...
PACS
2000
Springer
13 years 9 months ago
2000
Springer
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
FCCM
2008
IEEE
13 years 5 months ago
2008
IEEE
Communications infrastructure for modular reconfiguration of FPGAs needs to support the changing communications interfaces of a sequence of modules. In order to avoid the overhead...