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» Floorplan-aware automated synthesis of bus-based communicati...
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DAC
2005
ACM
14 years 4 months ago
Floorplan-aware automated synthesis of bus-based communication architectures
Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh...
DAC
2006
ACM
14 years 4 months ago
Communication latency aware low power NoC synthesis
Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham...
ICCAD
1998
IEEE
120views Hardware» more  ICCAD 1998»
13 years 7 months ago
Communication synthesis for distributed embedded systems
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
Ross B. Ortega, Gaetano Borriello
CODES
2006
IEEE
13 years 9 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...