45 search results - page 1 / 9 » Floorplanning with Pin Assignment |
ICCAD
1990
IEEE
13 years 9 months ago
1990
IEEE
We present a hierarchicaltechniquefor floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative po...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...
JETC
2008
13 years 3 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...