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» Forensic engineering techniques for VLSI CAD tools
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DAC
2000
ACM
14 years 5 months ago
Forensic engineering techniques for VLSI CAD tools
The proliferation of the Internet has a ected the business model of almost all semiconductor and VLSI CAD companies that rely on intellectual property (IP) as their main source of...
Darko Kirovski, David T. Liu, Jennifer L. Wong, Mi...
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
13 years 10 months ago
VLSI CAD tool protection by birthmarking design solutions
Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern...
Lin Yuan, Gang Qu, Ankur Srivastava
CCL
1994
Springer
13 years 8 months ago
Application of Constraint Logic Programming for VLSI CAD Tools
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
Renate Beckmann, Ulrich Bieker, Ingolf Markhof
DAC
2001
ACM
14 years 5 months ago
Publicly Detectable Techniques for the Protection of Virtual Components
Highlighted with the newly released intellectual property (IP) protection white paper by VSI Alliance, the protection of virtual components (VCs) has received a large amount of at...
Gang Qu
IH
2001
Springer
13 years 9 months ago
Computational Forensic Techniques for Intellectual Property Protection
Computational forensic engineering (CFE) aims to identify the entity that created a particular intellectual property (IP). Rather than relying on watermarking content or designs, t...
Jennifer L. Wong, Darko Kirovski, Miodrag Potkonja...