38 search results - page 7 / 8 » Formal verification of LTL formulas for SystemC designs |
POPL
2004
ACM
14 years 6 months ago
2004
ACM
We prove the decidability of the quantifier-free, static fragment of ambient logic, with composition adjunct and iteration, which corresponds to a kind of regular expression langu...
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
FASE
2008
Springer
13 years 7 months ago
2008
Springer
We introduce a logical verification framework for checking functional properties of service-oriented applications formally specified using the service specification language COWS. ...
FMCAD
2000
Springer
13 years 9 months ago
2000
Springer
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...