97 search results - page 1 / 20 » Formal verification of behavioral VHDL specifications: a cas... |
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
FORMATS
2007
Springer
13 years 8 months ago
2007
Springer
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
EUROMICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
In this paper we propose a high-level description of the behavior of digital systems. Behaviors are specified with a graphical synchronous model: “SyncCharts”. SyncCharts supp...
ACSC
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper presents a case study for automatic verification using the Communicating Sequential Processes formalism. The case study concerns the Futurebus+ cache coherency standard...
JSA
2008
13 years 3 months ago
2008
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...