97 search results - page 2 / 20 » Formal verification of behavioral VHDL specifications: a cas... |
FMCAD
2007
Springer
13 years 8 months ago
2007
Springer
Modeling hardware through atomic guard/action transitions with interleaving semantics is popular, owing to the conceptual clarity of modeling and verifying the high level behavior ...
CAV
2007
Springer
13 years 9 months ago
2007
Springer
Abstract. In this paper, we describe the features of the Timed Abstract State Machine toolset. The toolset implements the features of the Timed Abstract State Machine (TASM) langua...
IFM
2010
Springer
13 years 2 months ago
2010
Springer
In this paper we describe techniques for the specification and verification of model transformations using a combination of UML and formal methods. The use of UML 2 notations to s...
ASIAN
2009
Springer
13 years 6 months ago
2009
Springer
Abstract. Clever algorithm design is sometimes superseded by simple encodings into logic. We apply this motto to a few case studies in the formal verification of security propertie...
CORR
2008
Springer
13 years 5 months ago
2008
Springer
Synchronous languages rely on formal methods to ease the development of applications in an efficient and reusable way. Formal methods have been advocated as a means of increasing t...