Sciweavers

2 search results - page 1 / 1
» From Bit Level Systolic Arrays to HDTV Processor Chips
Sort
View
ASAP
2006
IEEE
119views Hardware» more  ASAP 2006»
13 years 6 months ago
From Bit Level Systolic Arrays to HDTV Processor Chips
The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on sys...
John V. McCanny, Roger F. Woods, John G. McWhirter
MVA
1992
143views Computer Vision» more  MVA 1992»
13 years 6 months ago
A Real-Time Vision System Using Integrated Memory Array Processor Prototype LSI
This study reports on the performance of a Real-Time Vision System (RVS) and its use of an IMAP prototype LSI. This LSI integrates eight 8 bit processors and a 144 Kbit SRAM on a ...
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro ...