68 search results - page 2 / 14 » From boolean to quantitative synthesis |
EMSOFT
2011
Springer
12 years 5 months ago
2011
Springer
Given a multi-modal dynamical system, optimal switching logic synthesis involves generating conditions for switching between the system modes such that the resulting hybrid system...
ACSD
2010
IEEE
13 years 3 months ago
2010
IEEE
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
ICCAD
2010
IEEE
13 years 3 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
FMCAD
2008
Springer
13 years 6 months ago
2008
Springer
Automatic techniques for software verification focus on obtaining witnesses of program failure. Such counterexamples often fail to localize the precise cause of an error and usuall...