27 search results - page 1 / 6 » Fully polynomial time approximation schemes for stochastic d... |
SODA
2008
ACM
13 years 6 months ago
2008
ACM
We develop a framework for obtaining Fully Polynomial Time Approximation Schemes (FPTASs) for stochastic univariate dynamic programs with either convex or monotone single-period c...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
ISPD
2009
ACM
13 years 11 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
JCO
2011
12 years 11 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...