174 search results - page 3 / 35 » Functional Test Generation for Full Scan Circuits |
ICCD
2006
IEEE
13 years 11 months ago
2006
IEEE
—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose t...
ICCAD
1996
IEEE
13 years 10 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
VTS
1997
IEEE
13 years 10 months ago
1997
IEEE
We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropos...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents a new method of selecting scan
ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...