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ICCD
2006
IEEE
105views Hardware» more  ICCD 2006»
14 years 4 months ago
A New Class of Sequential Circuits with Acyclic Test Generation Complexity
—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose t...
Chia Yee Ooi, Hideo Fujiwara
ICCAD
1996
IEEE
121views Hardware» more  ICCAD 1996»
14 years 2 months ago
Identification of unsettable flip-flops for partial scan and faster ATPG
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
ICCAD
2002
IEEE
116views Hardware» more  ICCAD 2002»
14 years 7 months ago
Conflict driven techniques for improving deterministic test pattern generation
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xiji...
VTS
1997
IEEE
105views Hardware» more  VTS 1997»
14 years 3 months ago
Critical hazard free test generation for asynchronous circuits
We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropos...
Ajay Khoche, Erik Brunvand
ICCAD
1994
IEEE
112views Hardware» more  ICCAD 1994»
14 years 2 months ago
Selecting partial scan flip-flops for circuit partitioning
This paper presents a new method of selecting scan ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
Toshinobu Ono