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APCSAC
2006
IEEE
13 years 10 months ago
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
Lih Wen Koh, Oliver Diessel
CASES
2001
ACM
13 years 8 months ago
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, ...
CASES
2009
ACM
13 years 10 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke