171 search results - page 1 / 35 » Future Performance Challenges in Nanometer Design |
DAC
2001
ACM
14 years 5 months ago
2001
ACM
We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power ...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLS...
VLSID
2006
IEEE
14 years 4 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical des...
VLSID
2004
IEEE
14 years 4 months ago
2004
IEEE
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...