2 search results - page 1 / 1 » GARNET: A detailed on-chip network model inside a full-syste... |
ISPASS
2009
IEEE
13 years 11 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
ISPASS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...