2 search results - page 1 / 1 » Gate-level aged timing simulation methodology for hot-carrie... |
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
- This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a un...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...