22 search results - page 4 / 5 » General Methodology for Soft-Error-Aware Power Optimization ... |
DAC
2009
ACM
14 years 5 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
EUROPAR
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
ISLPED
2006
ACM
13 years 10 months ago
2006
ACM
As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (D...